## (Solved) I need this MIPS questions answered according to the

I need this MIPS questions answered according to the instructions.Please I need it quick.Don't waste my time and end up giving wrong answers.Thanks.

A. (5 pt) Describe the condition for an overflow to occur when executing MIPS

instruction add \$s0, \$s1, \$s2 .

B. (10 pt) Instead of using a special hardware multiplier, it is possible to multiply using

shift instructions and add instructions. This is particularly attractive when multiplying

by small constants. Suppose we want to put 9 times the value of \$s2 into \$s3 ignoring

any overflow that may occur. Give the minimal sequence of MIPS instructions to

perform \$s3 \$s2 * 9 using only add instructions and shift instructions. As a

reminder the syntax for the MIPS shift left logical (sll) instruction is

sll

C.

\$t2, \$s0, 8

#\$t2 = \$s0 &lt;&lt; 8 bits

(10 pt) For the VHDL implementation of a full adder shown below, when do the

outputs cout and S settle at their final values (consider the worst case timing path with

the worst case inputs)?

signal t1, t2, t3, t4, t5: std_logic;

begin

t1 &lt;= not A after 1 ns;

t2 &lt;= not cin after 1 ns;

t4 &lt;= not((A or cin) and B) after 2 ns;

t3 &lt;= not((t1 or t2) and (A or cin)) after 2 ns;

t5 &lt;= t3 nand B after 2 ns;

S &lt;= not((B or t3) and t5) after 2 ns;

cout &lt;= not(t1 or t2) and t4) after 2 ns;

end concurrent_behavior;

cout ?

Page 1 of 7

S?

D. (3 pt) Give the key disadvantage of the single cycle MIPS datapath design?

E.

(3 pt) What decimal number does this two?s complement binary number represent:

1111 1111 1111 1111 1111 1111 1111 1111two?

F.

(9 pt) Assume that the operation times for the major functional units in the single-cycle

implementation of the MIPS datapath are the following:

Memory Units: 2ns

ALU: 2ns

Assuming that the multiplexors, control unit, PC accesses, sign extension unit,

and wires have no delay, what would be the minimum cycle time? (Hint: You

may want to refer to the datapath shown on page 8).

(30 pts) 3. ALU Design

Consider a 4-bit version of MIPS ALU shown on the next page. Here add/subt

place and op selects the multiplexor output (assume that the top input is selected by

an op of 000, etc.). Assume that it takes

2

4

6

8

ticks for a 2-input and, or, xor, nor to settle at its final output

ticks for a 4-input nor to settle at its final output

ticks for a 6-input multiplexor to settle at its final output

ticks from the latest arriving input for the sum and carry outputs

of a 1-bit full adder to settle at their final output

When do the result outputs settle at their final values for the inputs shown below

(ignoring the test for zero and for overflow)?

Page 2 of 7

op = 000

A = 1111

B = 0001

outputs settle at tick ____________ (3 pt)

To what MIPS instruction does this control setting correspond to? (You do not need

to write down the formal instruction,op rather, something like A+B will do)

______________________________________________________(3 pt)

A0

When do the result outputs settle at their final values for the inputs shown below

(ignoring the test for zero and for overflow)? result0

B0

op = 100

A = 1111

less

B = 0001

+

outputs settle at tick _____________ (3 pt)

A

What is the zero 1output value for this set of inputs? ________________ (3 pt)

Does this operation overflow? _________

+

B1

0

result

If so,1 why; if not, why not?(3 pt)

zero

less

A2

+

B2

0

result2

less

A3

result3

+

B3

0

set

less

Page 3 of 7

overflow

When do the result outputs settle at their final values for the inputs shown below

(ignoring the test for zero and for overflow)?

op = 101

A = 1111

B = 0000

outputs settle at tick _____________ (3 pt)

What is the zero output value for this set of inputs? __________________ (2 pt)

To what MIPS instruction does this control setting correspond to?

____________________________________________________________ (3 pt)

With the ALU design described in class (and shown in its 4-bit version on the

previous page) we assumed that a subtraction operation had to be performed as part

of the beq instruction. This would mean that we would have to wait for the

Page 4 of 7

subtraction operation to complete before selecting the output of the adder (through

the multiplexor) and then testing the result bits for all zero.

Is there a way to do it faster (with the hardware shown)? _____________ (1 pt)

If so, what would be the control bit setting for your new approach? (3 pt)

With the timing model given, how long would it take for the zero output to settle

using your new approach to beq? (3pt)

outputs settle at tick ________________

(30 pts) 4. Single Cycle Datapath Design

Give the setting for the control signals for the single cycle datapath shown on the

next page when executing a sw instruction. (10 pt)

Control Signal

RegDst

Jump

Branch

MemtoReg

Setting

X

0

0

X

X

Control Signal

ALUOp1

ALUOp0

MemWrite

ALUSrc

RegWrite

Setting

0

0

1

1

0

Your task is now to augment this single cycle MIPS datapath so that it can also

perform the instruction jalr (jump and link register) as defined below.

jalr

001111

rs

rs, rd

00000

Page 5 of 7

rd

00000

000000

Its functioning is to cause the datapath to unconditionally jump to the instruction

whose address is in register rs and to save the address of the next instruction (the

instruction following the jalr instruction in the code) in the register rd.

0

MemtoReg

1

1

Augment the single cycle MIPS datapath shown on the next page to also handle the

interconnects, and additional 1-bit control signals. Mark a line that is no longer

connected with an X somewhere along its length where the disconnect should occur.

(7pt) on figure

Write Data

ALU

control

Instr[5-0]

32

Sign

Extend

x

1

Instr[15-0]

16

Write Data

1

Instr[15 11]

0

Instr[31-0]

PC

Page 6 of 7

1

Data 2

0

ALU

Data 1

Register

File

Instr[20-16]

Instr[25-21]

4

Instruction

Memory

RegDst

ALUOp

Instr[31-26]

Control

RegWrite

ALUSrc

Branch

Jump

Shift

left 2

26

Instr[25-0]

Data

Memory

overflow

Shift

left 2

PC+4[31 -28]

32

28

x

zero

MemWrite

1

0

PCSrc

0

1

What new control signal(s) did you need to add and explain their basic function.

(3 pt)

Give the setting for all the control signals (both previously existing and the one(s)

you added) to execute the jalr. (10 pt)

Control Signal

RegDst

Jump

Branch

MemtoReg

ALUOp1

ALUOp0

Setting

1

X

X

X

X

X

X

Control Signal

MemWrite

ALUSrc

RegWrite

Page 7 of 7

Setting

0

X

1

1

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